How to build faster microprocessor is always a hot research spot. The era of achieving speedup by simply increasing clock frequency has long been over, in the recent decades people placed more and more focus on achieving parallelism, both instruction-level and thread-level, to get more speedup.
As the number of transistor that can be placed on a single chip increases to one billion, researchers argue about several ways to build faster microprocessor. In this paper, it introduces an evolutionary architecture design to achieve both instruction-level and thread-level parallelism. ...
Instruction fetch unit has different effects on the performance. ...
Context switch is an important factor to consider. Since instructions from different threads are executing simultaneously in the pipeline, we need to evaluate the cost of context switch. ....
SMT needs support from operating system. ...
SMT introduces a good model to exploit both instruction-level and thread-level parallelism. Multiprogramming and parallel application will benefit a lot from SMT, as the simulation result in this paper shows. However, SMT still doesn't solve the problem of how to speedup a conventional, single-threaded program. ...
SMT and CMP are not always irrelevant. SMT can be a building block for CMP, as Sun Niagara does, who has 8 cores and each core is a 4-thread SMT processor. ...
Labels: America, Research, U of M
